Several types of memory devices, such as Flash memories, use arrays of analog memory cells for storing data. Each analog memory cell stores a quantity of an analog value, also referred to as a storage value, such as an electrical charge or voltage. The storage value represents the information stored in the cell. In Flash memories, for example, each analog memory cell holds a certain amount of electrical charge. The range of possible analog values is typically divided into regions, each region corresponding to one or more data bit values. Data is written to an analog memory cell by writing a nominal analog value that corresponds to the desired bit or bits.
Some memory devices, which are commonly referred to as Single-Level Cell (SLC) devices, store a single bit of information in each memory cell, i.e., each memory cell can be programmed to assume two possible memory states. Higher-density devices, often referred to as Multi-Level Cell (MLC) devices, store two or more bits per memory cell, i.e., can be programmed to assume more than two possible memory states.
Flash memory devices are described, for example, by Bez et al., in “Introduction to Flash Memory,” Proceedings of the IEEE, volume 91, number 4, April, 2003, pages 489-502, which is incorporated herein by reference. Multi-level Flash cells and devices are described, for example, by Eitan et al., in “Multilevel Flash Cells and their Trade-Offs,” Proceedings of the 1996 IEEE International Electron Devices Meeting (IEDM), New York, N.Y., pages 169-172, which is incorporated herein by reference. The paper compares several kinds of multilevel Flash cells, such as common ground, DINOR, AND, NOR and NAND cells.
Eitan et al., describe another type of analog memory cell called Nitride Read Only Memory (NROM) in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cells?” Proceedings of the 1999 International Conference on Solid State Devices and Materials (SSDM), Tokyo, Japan, Sep. 21-24, 1999, pages 522-524, which is incorporated herein by reference. NROM cells are also described by Maayan et al., in “A 512 Mb NROM Flash Data Storage Memory with 8 MB/s Data Rate”, Proceedings of the 2002 IEEE International Solid-State Circuits Conference (ISSCC 2002), San Francisco, Calif., Feb. 3-7, 2002, pages 100-101, which is incorporated herein by reference. Other exemplary types of analog memory cells are Floating Gate (FG) cells, Ferroelectric RAM (FRAM) cells, magnetic RAM (MRAM) cells, Charge Trap Flash (CTF) and phase change RAM (PRAM, also referred to as Phase Change Memory—PCM) cells. FRAM, MRAM and PRAM cells are described, for example, by Kim and Koh in “Future Memory Technology including Emerging New Memories,” Proceedings of the 24th International Conference on Microelectronics (MIEL), Nis, Serbia and Montenegro, May 16-19, 2004, volume 1, pages 377-384, which is incorporated herein by reference.
The storage values held in analog memory cells are sometimes distorted by cross-coupling interference from other memory cells. Various techniques for reducing cross-coupling effects are known in the art. For example, PCT International Publication WO 2007/132453, whose disclosure is incorporated herein by reference, describes a method for operating a memory. Data is stored in a group of analog memory cells as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.
As another example, PCT International Publication WO 2007/132457, whose disclosure is incorporated herein by reference, describes a method for operating a memory device. Data is encoded using an Error Correction Code (ECC) and the encoded data is stored as first analog values in respective analog memory cells of the memory device. After storing the encoded data, second analog values are read from the respective memory cells in which the encoded data were stored. At least some of the second analog values differ from the respective first analog values. A distortion that is present in the second analog values is estimated. Error correction metrics are computed with respect to the second analog values responsively to the estimated distortion. The second analog values are processed using the error correction metrics in an ECC decoding process, so as to reconstruct the data.
Analog memory cell arrays are typically divided into pages, such that data is written to or read from the memory cells of a given page simultaneously. Some known techniques, however, access memory cells at a finer granularity. For example, U.S. Patent Application Publication 2006/0271748, whose disclosure is incorporated herein by reference, describes systems and methods for memory management. The disclosed methods detect a request to activate a memory portion, which is limited in size to a partial page size, where the partial page size is less than a full page size associated with the memory. In one embodiment, detecting the request includes identifying a row address and partial page address associated with the request, where the partial page address indicates that the memory portion is to be limited to the partial page size.
U.S. Pat. No. 6,101,614, whose disclosure is incorporated herein by reference, describes a method and apparatus for automatically scrubbing Error Correction Code (ECC) errors in memory upon the detection of a correctable error in data read from memory. A memory controller includes memory control logic for controlling accesses to memory, an ECC error checking and correcting unit for checking data read from memory for errors and for correcting any correctable errors found in the read data, a first data buffer for storing the corrected read data output from the ECC error checking and correcting unit, and a write-back path having an input end coupled to an output of the first data buffer and an output end coupled to memory. Upon the detection of a correctable error in data read from a particular memory location, the ECC error checking and correcting unit signals to the memory control logic the existence of a correctable error in the read data. The memory control logic then obtains exclusive control over the first data buffer and the write-back path to control writing of the corrected read data onto the write-back path and subsequently to memory.
Data is often read from analog memory cells by comparing the storage values of the cells to one or more read thresholds. In some known methods, the cells are read using multiple read thresholds. For example, PCT International Publication WO 2008/053472, whose disclosure is incorporated herein by reference, describes a method for operating a memory that includes multiple analog memory cells. The method includes storing data, which is encoded with an ECC, in the analog memory cells by writing respective analog input values selected from a set of nominal values to the cells. The stored data is read by performing multiple read operations that compare analog output values of the analog memory cells to different, respective read thresholds so as to produce multiple comparison results for each of the analog memory cells. Soft metrics are computed responsively to the multiple comparison results. The ECC is decoded using the soft metrics, so as to extract the data stored in the analog memory cells.